The present invention relates to the field of digital processing systems with diagnostic capabilities. More specifically, in one embodiment, the invention provides a means for scanning scannable processor circuitry without disturbing a nonscannable microprocessor which forms part of a digital system.
To fully diagnose a logic-only circuit (i.e., no memory of past states), a diagnostic system need only control the overall inputs to the circuit, and record the outputs. The outputs for a known set of inputs, when compared to an expected set of outputs, will indicate whether the circuit is working properly. Circuits with memory elements, such as flip-flops, latches, and memory storage cells, are more complicated to diagnose.
To fully diagnose circuits with memory elements, not only must the inputs be controlled, but the internally remembered states must be known and controllable. Some internal states can be controlled by manipulation of the inputs to the circuit. For example, the internal state of a counter, i.e., its count, can be controlled by asserting a reset input of the counter to reach a known state, then clocking the clock input to reach the desired internal state. This, of course, is not practical with today's complex circuits. Furthermore, for certain tests, the internal state might need to be set to a state which is not reachable through mere manipulation of the circuit's inputs.
What is needed is a means for reading the internal state of the circuit and for setting the internal state to a specific state. With discrete circuitry, an internal state can be done by probing each memory element and setting a known state can be set by gating off each memory element output and substituting a logic value consistent with the desired internal state. With integrated circuitry, however, the number of pins over which signals can be communicated between a test system and the integrated circuit severely limits the number of pins which can be allocated to internal state testing and control.
One well-known method of dealing with diagnostics in integrated circuits (IC's) is to include a scan path among the logic of the circuit. A scan path is a serial path linking all the memory elements of a circuit, or at least those which are to be scannable elements, into a serial stream. Placing the elements in a serial scan path allows the internal state to be read serially from one pin, and allows the internal state to be set with one pin.
The integrated circuit has a mechanism for switching from a normal circuit operation mode to a test mode. In the normal circuit operation mode, a memory element is responsive to its inputs, and in a test mode, the memory element is responsive to data passing along the scan path. Consequently, shifting data into and out of the scan path will cause the outputs of the memory element to change as the data shifts by. If the memory element is one which directly affects the output of the circuit, the shifting of test data on the scan path will appear as data rippling over the outputs of the circuit.
To set the circuit to a known state (scan in), settings for each memory element in the scan path are scanned into a scan input, and to read the state of the circuit (scan out), data is read from a scan path output. The scan in and scan out is performed by clocking the scan path by a number of clocks equal to the number of memory elements in the scan path. Of course, a scan enable must be provided, which when not asserted allows for normal operation of the circuit. Thus, in normal operation, the circuit behaves as designed, and when the scan enable is asserted, the circuit behaves as a serial register encompassing all the diagnosable memory elements.
FIG. 1 illustrates this concept. FIG. 1 shows a parallel register 10, with 8 bits of data input, 8 bits of data output, a clock input, an input for a scan enable signal, a scan data input, and a scan data output. Register 10 operates as a register when the scan enable signal is not asserted, with data passing from the inputs I.sub.0 -I.sub.7 to the outputs O.sub.0 -O.sub.7 with the clock.
When a scan enable signal is asserted, the data inputs no longer affect the data outputs. Instead, the data outputs are affected by the data scanned into the register via the scan data input using the clock. The current internal state of register 10 is read out at the scan data output. This scanning process presents a problem where register 10 is part of a larger system. Suppose register 10 contains all zeros, and "10000000" is to be scanned in, where the "1" is to end up as bit 7. Because the scan input is coupled to bit 0, the "1" will ripple through each of the outputs as it is being clocked in, thus disturbing any circuit element which depends on the output of register 10, thereby disturbing the states of other circuits.
One solution to the problem of output rippling of register 10 is to place another 8-bit nonscannable latch at the output of register 10, and not clock that latch while a scan is occurring, thus shielding any dependent circuit elements from register 10. However, this leaves no way of testing the now-added nonscannable latch.
Another solution is to coordinate the scan of register 10 with the scan of the dependent elements. However, where the dependent elements are not scannable, such as where the dependent element is an enclosed IC provided by another manufacturer, this solution is not possible.
From the above it is seen that an improved means is needed for scanning a circuit which has dependencies in a nonscannable circuit, such as a microprocessor, without disturbing the operation of those dependent circuits.